Pin Configuration

Pinout table

The RPi Camera FMC has a low pin count FPGA Mezzanine Card (FMC) connector, providing the connections to the FPGA on the development board. The following table defines the pinout of the FMC connector and describes each pin’s purpose on this mezzanine card.

Pin	Pin name	Net	Description
C1	GND	GND	Ground
C2	DP0_C2M_P	DP0_C2M_P	Not used
C3	DP0_C2M_N	DP0_C2M_N	Not used
C4	GND	GND	Ground
C5	GND	GND	Ground
C6	DP0_M2C_P	DP0_M2C_P	Not used
C7	DP0_M2C_N	DP0_M2C_N	Not used
C8	GND	GND	Ground
C9	GND	GND	Ground
C10	LA06_P	CAM0_DATA0_P	Camera 0 Data lane 0 Positive
C11	LA06_N	CAM0_DATA0_N	Camera 0 Data lane 0 Negative
C12	GND	GND	Ground
C13	GND	GND	Ground
C14	LA10_P	STB_LA10_P	Not connected, reserved for strobe propagation
C15	LA10_N	STB_LA10_N	Not connected, reserved for strobe propagation
C16	GND	GND	Ground
C17	GND	GND	Ground
C18	LA14_P	CAM1_DATA1_P	Camera 1 Data lane 1 Positive
C19	LA14_N	CAM1_DATA1_N	Camera 1 Data lane 1 Negative
C20	GND	GND	Ground
C21	GND	GND	Ground
C22	LA18_P_CC	CAM2_CLK_P	Camera 2 Clock lane Positive
C23	LA18_N_CC	CAM2_CLK_N	Camera 2 Clock lane Negative
C24	GND	GND	Ground
C25	GND	GND	Ground
C26	LA27_P	CAM_IO0_OE_N	Camera IO0 Output enable (active low)
C27	LA27_N	CAM_IO1_OE_N	Camera IO1 Output enable (active low)
C28	GND	GND	Ground
C29	GND	GND	Ground
C30	SCL	I2C_SCL	I2C Clock (FPGA-to-PHY)
C31	SDA	I2C_SDA	I2C Data (bidirectional)
C32	GND	GND	Ground
C33	GND	GND	Ground
C34	GA0	GA0	EEPROM Address Bit 1 (A1)
C35	12P0V_1	12V0	12VDC (Not used)
C36	GND	GND	Ground
C37	12P0V_2	12V0	12VDC (Not used)
C38	GND	GND	Ground
C39	3P3V_1	3V3	3.3VDC
C40	GND	GND	Ground
D1	PG_C2M	PG	Power Good (Driven by carrier)
D2	GND	GND	Ground
D3	GND	GND	Ground
D4	GBTCLK0_M2C_P	N/C	Not used
D5	GBTCLK0_M2C_N	N/C	Not used
D6	GND	GND	Ground
D7	GND	GND	Ground
D8	LA01_P_CC	CAM1_LA01_CLK_P	Camera 1 Clock lane via LA01 Positive
D9	LA01_N_CC	CAM1_LA01_CLK_N	Camera 1 Clock lane via LA01 Negative
D10	GND	GND	Ground
D11	LA05_P	CAM1_SDA	Camera 1 I2C bus data
D12	LA05_N	CAM1_SCL	Camera 1 I2C bus clock
D13	GND	GND	Ground
D14	LA09_P	CAM1_IO1	Camera 1 IO1 (GPIO)
D15	LA09_N	CAM1_IO0	Camera 1 IO0 (GPIO)
D16	GND	GND	Ground
D17	LA13_P	CAM_IO0_DIR	Camera IO0 Direction select
D18	LA13_N	CAM_IO1_DIR	Camera IO1 Direction select
D19	GND	GND	Ground
D20	LA17_P_CC	CAM2_DATA1_P	Camera 2 Data lane 1 Positive
D21	LA17_N_CC	CAM2_DATA1_N	Camera 2 Data lane 1 Negative
D22	GND	GND	Ground
D23	LA23_P	STB_LA23_P	Not connected, reserved for strobe propagation
D24	LA23_N	STB_LA23_N	Not connected, reserved for strobe propagation
D25	GND	GND	Ground
D26	LA26_P	CAM3_LA26_CLK_P	Camera 3 Clock lane via LA26 Positive
D27	LA26_N	CAM3_LA26_CLK_N	Camera 3 Clock lane via LA26 Negative
D28	GND	GND	Ground
D29	TCK	N/C	Not used
D30	TDI	TDI-TDO	JTAG TDI (Connects to TDO to close JTAG chain)
D31	TDO	TDI-TDO	JTAG TDO (Connects to TDI to close JTAG chain)
D32	3P3VAUX	3V3AUX	3.3VDC Power supply for EEPROM
D33	TMS	N/C	Not used
D34	TRST_L	N/C	Not used
D35	GA1	GA1	EEPROM Address Bit 0 (A0)
D36	3P3V_2	3V3	3.3VDC
D37	GND	GND	Ground
D38	3P3V_3	3V3	3.3VDC
D39	GND	GND	Ground
D40	3P3V_4	3V3	3.3VDC
G1	GND	GND	Ground
G2	CLK1_M2C_P	CLK1_M2C_P	Not used
G3	CLK1_M2C_N	CLK1_M2C_N	Not used
G4	GND	GND	Ground
G5	GND	GND	Ground
G6	LA00_P_CC	CAM0_CLK_P	Camera 0 Clock lane Positive
G7	LA00_N_CC	CAM0_CLK_N	Camera 0 Clock lane Negative
G8	GND	GND	Ground
G9	LA03_P	CAM0_SDA	Camera 0 I2C bus data
G10	LA03_N	CAM0_SCL	Camera 0 I2C bus clock
G11	GND	GND	Ground
G12	LA08_P	STB_LA08_P	Not connected, reserved for strobe propagation
G13	LA08_N	STB_LA08_N	Not connected, reserved for strobe propagation
G14	GND	GND	Ground
G15	LA12_P	CAM0_IO1	Camera 0 IO1 (GPIO)
G16	LA12_N	CAM0_IO0	Camera 0 IO0 (GPIO)
G17	GND	GND	Ground
G18	LA16_P	CAM1_LA16_CLK_P	Camera 1 Clock lane via LA16 Positive
G19	LA16_N	CAM1_LA16_CLK_N	Camera 1 Clock lane via LA16 Negative
G20	GND	GND	Ground
G21	LA20_P	CAM3_IO1	Camera 3 IO1 (GPIO)
G22	LA20_N	CAM3_IO0	Camera 3 IO0 (GPIO)
G23	GND	GND	Ground
G24	LA22_P	STB_LA22_P	Not connected, reserved for strobe propagation
G25	LA22_N	STB_LA22_N	Not connected, reserved for strobe propagation
G26	GND	GND	Ground
G27	LA25_P	CAM3_CLK_SEL	Camera 3 Clock select (0=LA26,1=LA31)
G28	LA25_N	CAM1_CLK_SEL	Camera 1 Clock select (0=LA01,1=LA16)
G29	GND	GND	Ground
G30	LA29_P	N/C	Not used
G31	LA29_N	N/C	Not used
G32	GND	GND	Ground
G33	LA31_P	CAM3_LA31_CLK_P	Camera 3 Clock lane via LA31 Positive
G34	LA31_N	CAM3_LA31_CLK_N	Camera 3 Clock lane via LA31 Negative
G35	GND	GND	Ground
G36	LA33_P	CAM3_DATA0_P	Camera 3 Data lane 0 Positive
G37	LA33_N	CAM3_DATA0_N	Camera 3 Data lane 0 Negative
G38	GND	GND	Ground
G39	VADJ_3	VADJ	I/O Supply Voltage (1.2VDC)
G40	GND	GND	Ground
H1	VREF_A_M2C	N/C	Not used
H2	PRSNT_M2C_L	GND	Ground
H3	GND	GND	Ground
H4	CLK0_M2C_P	CLK0_M2C_P	Not used
H5	CLK0_M2C_N	CLK0_M2C_N	Not used
H6	GND	GND	Ground
H7	LA02_P	CAM0_DATA1_P	Camera 0 Data lane 1 Positive
H8	LA02_N	CAM0_DATA1_N	Camera 0 Data lane 1 Negative
H9	GND	GND	Ground
H10	LA04_P	N/C	Not used
H11	LA04_N	N/C	Not used
H12	GND	GND	Ground
H13	LA07_P	N/C	Not used
H14	LA07_N	N/C	Not used
H15	GND	GND	Ground
H16	LA11_P	STB_LA11_P	Not connected, reserved for strobe propagation
H17	LA11_N	STB_LA11_N	Not connected, reserved for strobe propagation
H18	GND	GND	Ground
H19	LA15_P	CAM1_DATA0_P	Camera 1 Data lane 0 Positive
H20	LA15_N	CAM1_DATA0_N	Camera 1 Data lane 0 Negative
H21	GND	GND	Ground
H22	LA19_P	CAM2_IO1	Camera 2 IO1 (GPIO)
H23	LA19_N	CAM2_IO0	Camera 2 IO0 (GPIO)
H24	GND	GND	Ground
H25	LA21_P	STB_LA21_P	Not connected, reserved for strobe propagation
H26	LA21_N	STB_LA21_N	Not connected, reserved for strobe propagation
H27	GND	GND	Ground
H28	LA24_P	CAM2_DATA0_P	Camera 2 Data lane 0 Positive
H29	LA24_N	CAM2_DATA0_N	Camera 2 Data lane 0 Negative
H30	GND	GND	Ground
H31	LA28_P	CAM3_DATA1_P	Camera 3 Data lane 1 Positive
H32	LA28_N	CAM3_DATA1_N	Camera 3 Data lane 1 Negative
H33	GND	GND	Ground
H34	LA30_P	CAM2_SDA	Camera 2 I2C bus data
H35	LA30_N	CAM2_SCL	Camera 2 I2C bus clock
H36	GND	GND	Ground
H37	LA32_P	CAM3_SDA	Camera 3 I2C bus data
H38	LA32_N	CAM3_SCL	Camera 3 I2C bus clock
H39	GND	GND	Ground
H40	VADJ_4	VADJ	I/O Supply Voltage (1.2VDC)

Camera 0

FMC pins relevant to the port labelled CAM0:

Pin	Pin name	Net	Description
G6	LA00_P_CC	CAM0_CLK_P	Camera 0 Clock lane Positive
G7	LA00_N_CC	CAM0_CLK_N	Camera 0 Clock lane Negative
C10	LA06_P	CAM0_DATA0_P	Camera 0 Data lane 0 Positive
C11	LA06_N	CAM0_DATA0_N	Camera 0 Data lane 0 Negative
H7	LA02_P	CAM0_DATA1_P	Camera 0 Data lane 1 Positive
H8	LA02_N	CAM0_DATA1_N	Camera 0 Data lane 1 Negative
G9	LA03_P	CAM0_SDA	Camera 0 I2C bus data
G10	LA03_N	CAM0_SCL	Camera 0 I2C bus clock
G15	LA12_P	CAM0_IO1	Camera 0 IO1 (GPIO)
G16	LA12_N	CAM0_IO0	Camera 0 IO0 (GPIO)

Camera 1

FMC pins relevant to the port labelled CAM1:

Pin	Pin name	Net	Description
D8	LA01_P_CC	CAM1_LA01_CLK_P	Camera 1 Clock lane via LA01 Positive
D9	LA01_N_CC	CAM1_LA01_CLK_N	Camera 1 Clock lane via LA01 Negative
G18	LA16_P	CAM1_LA16_CLK_P	Camera 1 Clock lane via LA16 Positive
G19	LA16_N	CAM1_LA16_CLK_N	Camera 1 Clock lane via LA16 Negative
H19	LA15_P	CAM1_DATA0_P	Camera 1 Data lane 0 Positive
H20	LA15_N	CAM1_DATA0_N	Camera 1 Data lane 0 Negative
C18	LA14_P	CAM1_DATA1_P	Camera 1 Data lane 1 Positive
C19	LA14_N	CAM1_DATA1_N	Camera 1 Data lane 1 Negative
D11	LA05_P	CAM1_SDA	Camera 1 I2C bus data
D12	LA05_N	CAM1_SCL	Camera 1 I2C bus clock
D14	LA09_P	CAM1_IO1	Camera 1 IO1 (GPIO)
D15	LA09_N	CAM1_IO0	Camera 1 IO0 (GPIO)
G28	LA25_N	CAM1_CLK_SEL	Camera 1 Clock select (0=LA01,1=LA16)

Note: The clock for this camera must be connected to either LA01_P/N_CC or LA16_P/N.

Camera 2

FMC pins relevant to the port labelled CAM2:

Pin	Pin name	Net	Description
C22	LA18_P_CC	CAM2_CLK_P	Camera 2 Clock lane Positive
C23	LA18_N_CC	CAM2_CLK_N	Camera 2 Clock lane Negative
H28	LA24_P	CAM2_DATA0_P	Camera 2 Data lane 0 Positive
H29	LA24_N	CAM2_DATA0_N	Camera 2 Data lane 0 Negative
D20	LA17_P_CC	CAM2_DATA1_P	Camera 2 Data lane 1 Positive
D21	LA17_N_CC	CAM2_DATA1_N	Camera 2 Data lane 1 Negative
H34	LA30_P	CAM2_SDA	Camera 2 I2C bus data
H35	LA30_N	CAM2_SCL	Camera 2 I2C bus clock
H22	LA19_P	CAM2_IO1	Camera 2 IO1 (GPIO)
H23	LA19_N	CAM2_IO0	Camera 2 IO0 (GPIO)

Camera 3

FMC pins relevant to the port labelled CAM3:

Pin	Pin name	Net	Description
D26	LA26_P	CAM3_LA26_CLK_P	Camera 3 Clock lane via LA26 Positive
D27	LA26_N	CAM3_LA26_CLK_N	Camera 3 Clock lane via LA26 Negative
G33	LA31_P	CAM3_LA31_CLK_P	Camera 3 Clock lane via LA31 Positive
G34	LA31_N	CAM3_LA31_CLK_N	Camera 3 Clock lane via LA31 Negative
G36	LA33_P	CAM3_DATA0_P	Camera 3 Data lane 0 Positive
G37	LA33_N	CAM3_DATA0_N	Camera 3 Data lane 0 Negative
H31	LA28_P	CAM3_DATA1_P	Camera 3 Data lane 1 Positive
H32	LA28_N	CAM3_DATA1_N	Camera 3 Data lane 1 Negative
H37	LA32_P	CAM3_SDA	Camera 3 I2C bus data
H38	LA32_N	CAM3_SCL	Camera 3 I2C bus clock
G21	LA20_P	CAM3_IO1	Camera 3 IO1 (GPIO)
G22	LA20_N	CAM3_IO0	Camera 3 IO0 (GPIO)
G27	LA25_P	CAM3_CLK_SEL	Camera 3 Clock select (0=LA26,1=LA31)

Note: The clock for this camera must be connected to either LA26_P/N or LA31_P/N.

Net lengths

The table below lists the critical trace lengths.

	Net	Length (mils)
Camera 0	CAM0_CLK_N	1506.42
	CAM0_CLK_P	1506.992
	CAM0_DATA0_N	1508.888
	CAM0_DATA0_P	1510.286
	CAM0_DATA1_N	1507.443
	CAM0_DATA1_P	1509.986
Camera 1	CAM1_LA01_CLK_N	1480.268
	CAM1_LA01_CLK_P	1480.153
	CAM1_LA16_CLK_N	1479.618
	CAM1_LA16_CLK_P	1479.503
	CAM1_DATA0_N	1482.367
	CAM1_DATA0_P	1479.931
	CAM1_DATA1_N	1475.515
	CAM1_DATA1_P	1478.691
Camera 2	CAM2_CLK_N	1513.183
	CAM2_CLK_P	1513.034
	CAM2_DATA0_N	1518.514
	CAM2_DATA0_P	1516.078
	CAM2_DATA1_N	1521.252
	CAM2_DATA1_P	1521.171
Camera 3	CAM3_LA26_CLK_N	1625.862
	CAM3_LA26_CLK_P	1622.853
	CAM3_LA31_CLK_N	1624.063
	CAM3_LA31_CLK_P	1621.055
	CAM3_DATA0_N	1627.619
	CAM3_DATA0_P	1623.909
	CAM3_DATA1_N	1622.79
	CAM3_DATA1_P	1621.035

Pin Configuration

Pinout table #

Camera 0 #

Camera 1 #

Camera 2 #

Camera 3 #

Net lengths #