Compatible Boards

The following development boards are compatible with the RPi Camera FMC.

Zynq Ultrascale+ boards

  • AMD Xilinx ZCU104 Zynq UltraScale+ Development board
  • AMD Xilinx ZCU102 Zynq UltraScale+ Development board
  • AMD Xilinx ZCU106 Zynq UltraScale+ Development board
  • TUL PYNQ-ZU Zynq UltraScale+ Development board
  • Digilent Genesys-ZU Zynq UltraScale+ Development board
  • Avnet UltraZed EV Carrier Zynq UltraScale+ Development board

Ultrascale+ boards

(coming soon)

Compatibility requirements

If you need to determine the compatibility of a development board that is not listed here, or you are designing a carrier board to mate with the RPi Camera FMC, please check your board against the list of requirements below.

VADJ

If you intend to use our example designs, or other designs that utilize the AMD Xilinx MIPI CSI Controller Subsystem IP , it is highly recommended that the development board have the ability to supply a VADJ voltage of 1.2VDC. If your development board uses a device from a manufacturer other than AMD Xilinx, the requirements for VADJ may be different; we suggest you refer to the documentation for the specific device and IP that you will be required to use. The RPi Camera FMC has an EEPROM containing IPMI data to be used by a power management device. If the development board has such a power management device, the correct VADJ will be applied automatically on power-up. Note that some development boards require the VADJ voltage to be configured by a DIP switch or jumper placement.

MIPI interfaces

Camera 0

  • FMC pins LA02, LA06, LA00 must be connected to the FPGA
  • Pin LA00 receives the MIPI clock and should be connected to a QBC or DBC clock capable pin
  • If LA00 is connected to a DBC pin, then LA02 and LA06 must be located in the same byte as the clock
  • All of the above pins must be connected to the same I/O bank

Camera 1

  • FMC pins LA14, LA15, and either LA01 or LA16 must be connected to the FPGA
  • Pin LA01 or LA16 receives the MIPI clock and should be connected to a QBC or DBC clock capable pin
  • If the chosen clock pin (LA00 or LA16) is connected to a DBC pin, then LA14 and LA15 must be located in the same byte as the clock
  • All of the above pins must be connected to the same I/O bank

Camera 2

  • FMC pins LA17, LA24, LA18 must be connected to the FPGA
  • Pin LA18 receives the MIPI clock and should be connected to a QBC or DBC clock capable pin
  • If LA18 is connected to a DBC pin, then LA17 and LA24 must be located in the same byte as the clock
  • All of the above pins must be connected to the same I/O bank

Camera 3

  • FMC pins LA28, LA33, and either LA26 or LA31 must be connected to the FPGA
  • Pin LA26 or LA31 receives the MIPI clock and should be connected to a QBC or DBC clock capable pin
  • If the chosen clock pin (LA26 or LA31) is connected to a DBC pin, then LA28 and LA33 must be located in the same byte as the clock
  • All of the above pins must be connected to the same I/O bank

Strobe propagation

It is advisable to group each camera’s MIPI pins (CLK, DATA0 and DATA1) into the same byte group; and if this is not possible, into two or three neighboring byte groups. The consequence of spreading a single camera’s MIPI pins over multiple byte groups, is that certain other pins in those byte groups will be required for strobe propagation. Strobe propagation renders pins unusable for other purposes, including for use by other cameras, therefore when selecting pins for multiple MIPI interfaces on a single I/O bank, it is essential to aim to minimize the need for strobe propagation pins.

Note that the use of pins for strobe propagation is a feature of the AMD Xilinx devices and the AMD Xilinx MIPI CSI Controller Subsystem IP . Strobe propagation and its limitations may not apply when using other devices or IP, and it is up to the board designer to check this before selecting a pin assignment.

I2C and GPIO

The following FMC pins must be connected to the FPGA for I2C and GPIO signals, however it is not critical into which I/O banks they are placed:

  • LA03_P/N
  • LA05_P/N
  • LA09_P/N
  • LA12_P/N
  • LA13_P/N
  • LA19_P/N
  • LA20_P/N
  • LA25_P/N
  • LA27_P/N
  • LA30_P/N
  • LA32_P/N

Note that these pins cannot be assigned to FPGA pins that are used for strobe propagation.

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